A gated D latch does not have ________.

The J-K flip-flop is a standard building block of clocked (sequential) logic circuits known as a ________.

Assume an latch, made from cross-coupled NAND gates, has a 0 on both inputs. The outputs will be ________.

The key to edge-triggered sequential circuits in VHDL is the ________.

In synchronous systems, the exact times at which any output can change state are determined by a signal commonly called the ________.