Exercise: Flip Flops

Questions for: Flip Flops

The toggle mode is the mode in which a(n) ________ changes states for each clock pulse.
A:
logic level
B:
flip-flop
C:
edge-detector circuit
D:
toggle detector
Answer: B
No answer description is available. Let's discuss.
📖
📝
💬
👁️
A gated S-R flip-flop is in the hold condition whenever ________.
A:
the Gate Enable is HIGH
B:
the Gate Enable is LOW
C:
the S and R inputs are both LOW
D:
the Gate Enable is HIGH and the S and R inputs are both LOW
Answer: D
No answer description is available. Let's discuss.
📖
📝
💬
👁️
The ________ is the time interval immediately following the active transition of the clock signal.
A:
hold time
B:
setup time
C:
over-time
D:
hang-time
Answer: A
No answer description is available. Let's discuss.
📖
📝
💬
👁️
The advantage of a J-K flip-flop over an S-R FF is that ________.
A:
it has fewer gates
B:
it has only one output
C:
it has no invalid states
D:
it does not require a clock input
Answer: C
No answer description is available. Let's discuss.
📖
📝
💬
👁️
The postponed symbol () on the output of a flip-flop identifies it as being ________.
A:
a D flip-flop
B:
a J-K flip-flop
C:
pulse triggered
D:
trailing edge-triggered
Answer: C
No answer description is available. Let's discuss.
📖
📝
💬
👁️
Ad Slot (Above Pagination)
Quiz