Exercise: Dc Biasing Fets

Questions for: Dc Biasing Fets

The input controlling variable for an FET transistor is a ________ level.
A:
resistor
B:
current
C:
voltage
D:
All of the above
Answer: C
No answer description is available. Let's discuss.
📖
📝
💬
👁️
________ must be considered in the total design process.
A:
Dc conditions
B:
Level of amplification
C:
Signal strength
D:
All of the above
Answer: D
No answer description is available. Let's discuss.
📖
📝
💬
👁️
In a universal JFET bias curve, the vertical scale labeled M is used for finding the solution to the ________ configuration.
A:
fixed-bias
B:
self-bias
C:
voltage-divider
D:
None of the above
Answer: C
No answer description is available. Let's discuss.
📖
📝
💬
👁️
The level of VDS is typically between ________ % and ________ % of VDD.
A:
0, 100
B:
10, 90
C:
25, 75
D:
None of the above
Answer: C
No answer description is available. Let's discuss.
📖
📝
💬
👁️
The controlled variable on the output side of an FET transistor is a ________ level.
A:
current
B:
voltage
C:
resistor
D:
None of the above
Answer: A
No answer description is available. Let's discuss.
📖
📝
💬
👁️
Ad Slot (Above Pagination)
Quiz