Exercise: Counters

Questions for: Counters

Which of the following is an invalid output state for an 8421 BCD counter?
A:
1110
B:
0000
C:
0010
D:
0001
Answer: A
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For a multistage counter to be truly synchronous, the ________ of each stage must be connected to ________.
A:
Cp, the same clock input line
B:
CE, the same clock input line
C:
, the terminal count output
D:
, both clock input lines
Answer: A
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Select the response that best describes the use of the Master Reset on typical 4-bit binary counters.
A:
When MR1 and MR2 are both HIGH, all Qs will be reset to zero.
B:
When MR1 and MR2 are both HIGH, all Qs will be reset to one.
C:
MR1 and MR2 are provided to synchronously reset all four flip-flops.
D:
To enable the count mode, MR1 and MR2 must be held LOW.
Answer: A
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The process of designing a synchronous counter that will count in a nonbinary manner is primarily based on:
A:
external logic circuits that decode the various states of the counter to apply the correct logic levels to the J-K inputs
B:
modifying BCD counters to change states on every second input clock pulse
C:
modifying asynchronous counters to change states on every second input clock pulse
D:
elimination of the counter stages and the addition of combinational logic circuits to produce the desired counts
Answer: A
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To operate correctly, starting a ring counter requires:
A:
clearing one flip-flop and presetting all the others.
B:
clearing all the flip-flops.
C:
presetting one flip-flop and clearing all the others.
D:
presetting all the flip-flops.
Answer: C
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