Exercise: Counters

Questions for: Counters

In a VHDL retriggerable edge-triggered one-shot, which condition will not exist when a clock edge occurs?
A:
A trigger edge has occurred and we must load the counter.
B:
The counter is zero and we need to keep it at zero.
C:
The shift register is reset.
D:
The counter is not zero and we need to count down by one.
Answer: C
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In an HDL ring counter, many invalid states are included in the programming by:
A:
using a case statement.
B:
using an elsif statement.
C:
including them under others.
D:
the ser_in line.
Answer: C
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The hexadecimal equivalent of 15,536 is ________.
A:
3CB0
B:
3C66
C:
63C0
D:
6300
Answer: A
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The terminal count of a 3-bit binary counter in the DOWN mode is ________.
A:
000
B:
111
C:
101
D:
010
Answer: A
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A 4-bit ripple counter consists of flip-flops, which each have a propagation delay from clock to Q output of 15 ns. For the counter to recycle from 1111 to 0000, it takes a total of ________.
A:
15 ns
B:
30 ns
C:
45 ns
D:
60 ns
Answer: D
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