A 4-bit PISO shift register that receives 4 bits of parallel data will shift to the ________ by ________ position(s) for each clock pulse.

Synchronous construction reduces the delay time of a counter to the delay of __________.

The modulus (mod) of a counter is the same as its maximum count (N).

A parallel-in, serial-out shift register enters all data bits simultaneously and transfers them out one bit at a time.

An asynchronous decade counter increases its value by ten for each clock pulse.