Exercise: Programmable Logic Device

Questions for: Programmable Logic Device

The final step in a design flow in which the logic design is implemented in the target device is called ________.
A:
design entry
B:
simulation
C:
downloading
D:
compiling
Answer: C
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A macrocell is ________.
A:
part of a PAL or GAL
B:
a type of one-time programmable SPLD
C:
an example of intellectual property
D:
a logic array block
Answer: A
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An EPM 7128S in a ________ PQFP package has 12 I/O per LAB plus 4 additional input-only pins for a total of 100 pins.
A:
100-pin
B:
120-pin
C:
140-pin
D:
160-pin
Answer: D
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Most FPGA logic modules utilize a(n) ________ approach to create the desired logic functions.
A:
AND array
B:
Look-up table
C:
OR array
D:
AND and OR array
Answer: B
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A GAL22V10 ________.
A:
has up to 32 inputs and 10 outputs
B:
is a type of SPLD
C:
has 10 inputs and 22 outputs
D:
is downloadable from the manufacturer's Web site
Answer: B
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