Exercise: Programmable Logic Device

Questions for: Programmable Logic Device

Design costs for standard cell ASICs are ________ those for MPGAs.
A:
lower than
B:
about the same as
C:
higher than
D:
none of the above
Answer: C
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A complex programmable logic device that consists of multiple SPLD arrays with programmable interconnections is called a ________.
A:
bed-of-nails
B:
boundary scan
C:
CLB
D:
CPLD
Answer: D
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The MAX+PLUS II compiler will automatically program a macrocell to borrow up to ________ product terms from each of the 3 adjacent macrocells in the same LAB.
A:
4
B:
5
C:
6
D:
7
Answer: B
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Gated arrays are ________ circuits that offer hundreds of thousands of gates.
A:
VLSI
B:
full custom
C:
LSI
D:
ULSI
Answer: D
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Full custom ICs can operate at ________ and require the ________.
A:
lowest speed, largest die area
B:
lowest speed, smallest die area
C:
highest speed, largest die area
D:
highest speed, smallest die area
Answer: D
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