Most PAL devices have a tristate buffer driving the input pins.

An expensive form of programmable logic is SPLD.

Schematic capture is a process performed by PLD software.

Gate arrays are ULSI circuits that offer hundreds of thousands of gates.

The PAL has an AND and OR structure similar to a PROM, but in the PAL the inputs to the AND gates are programmable, whereas the inputs to the OR gate are hard-wired.