A PAL consists of an array of fixed AND gates that are connected to a programmable array of OR gates.

In the OLMC of a GAL16V8, the FMUX selects the signal that is fed into the input matrix.

The four input-only pins found on devices in the MAX7000S family can be configured as specific high-speed control signals or as general user inputs.

PLDs cannot meet all the possible requirements of complex digital circuitry.

The Altera FLEX10K family uses a look-up table (LUT) architecture.