Exercise: Integrated Circuit Logic Families

Questions for: Integrated Circuit Logic Families

The propagation delay of standard TTL gates is approximately ________.
A:
2 s
B:
1 s
C:
4 ns
D:
10 ns
Answer: D
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The minimum input voltage recognized as HIGH by a TTL gate is ________.
A:
2.0 V
B:
2.4 V
C:
0.8 V
D:
5.0 V
Answer: A
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________ output levels would not be a valid LOW for a TTL gate.
A:
0.2 V
B:
0.3 V
C:
0.5 V
D:
All of the above.
Answer: D
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Propagation delay is important because ________.
A:
the logic gates must be given a short break during each clock cycle or else they will overheat
B:
it limits the maximum operating frequency of a gate
C:
it is a measure of how long the clock must be applied to the gate before it will make the required decision
D:
all the gates in a system must have the same propagation times in order to be compatible
Answer: A
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When the outputs of several open-collector TTL gates are connected together, the gate outputs ________.
A:
usually burn out
B:
produce more voltage
C:
are ANDed together
D:
produce more fan-out
Answer: C
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