The noise margin for TTL is 0.8 V.

The dc noise margins calculated using the proper values from a standard TTL data sheet are the worst-case margins. The typical dc noise margins are usually somewhat higher.

The major advantage of CMOS logic circuits over TTL is very low power consumption.

The data sheet for the 74 series of TTL ICs shows that V_cc has a range of 4.5 V to 5.5 V.

The major advantage of TTL logic circuits over CMOS is lower propagation delay.