Exercise: Field Effect Transistors

Questions for: Field Effect Transistors

Which JFET configuration would connect a high-resistance signal source to a low-resistance load?
A:
source follower
B:
common-source
C:
common-drain
D:
common-gate
Answer: A
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When an input signal reduces the channel size, the process is called:
A:
enhancement
B:
substrate connecting
C:
gate charge
D:
depletion
Answer: D
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With a 30-volt VDD, and an 8-kilohm drain resistor, what is the E-MOSFET Q point voltage, with ID = 3 mA?
A:
6 V
B:
10 V
C:
24 V
D:
30 V
Answer: A
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With the E-MOSFET, when gate input voltage is zero, drain current is:
A:
at saturation
B:
zero
C:
IDSS
D:
widening the channel
Answer: B
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A very simple bias for a D-MOSFET is called:
A:
self biasing
B:
gate biasing
C:
zero biasing
D:
voltage-divider biasing
Answer: C
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