Exercise: Digital System Projects Using Hdl

Questions for: Digital System Projects Using Hdl

In a digital clock application, the basic frequency must be divided down to:
A:
1 Hz.
B:
60 Hz.
C:
100 Hz.
D:
1000 Hz.
Answer: A
No answer description is available. Let's discuss.
📖
📝
💬
👁️
In an HDL application of a stepper motor, after an up/down counter is built what is done next?
A:
Build the sequencer
B:
Test it on a simulator
C:
Test the decoder
D:
Design an intermediate integer variable
Answer: B
No answer description is available. Let's discuss.
📖
📝
💬
👁️
How is the output frequency related to the sampling interval of a frequency counter?
A:
Directly with the sampling interval
B:
Inversely with the sampling interval
C:
More precision with longer sampling interval
D:
Less precision with longer sampling interval
Answer: C
No answer description is available. Let's discuss.
📖
📝
💬
👁️
In the digital clock project, when does the PM indicator go high?
A:
Never
B:
Going from 11:59:59 to 12:00:00
C:
Going from 12:59:59 to 01:00:00
D:
On the falling edge of the clock after enable goes high
Answer: B
No answer description is available. Let's discuss.
📖
📝
💬
👁️
In a frequency counter, what happens at high frequencies when the sampling interval is too long?
A:
The counter works fine.
B:
The counter undercounts the frequency.
C:
The measurement is less precise.
D:
The counter overflows.
Answer: D
No answer description is available. Let's discuss.
📖
📝
💬
👁️
Ad Slot (Above Pagination)
Quiz