Exercise: Digital System Projects Using Hdl

Questions for: Digital System Projects Using Hdl

In the keypad application, when all columns are HIGH, the ring counter is enabled and counting, and dav is LOW, what is the status of the d outputs?
A:
On
B:
Off
C:
Hi-Z
D:
1011
Answer: C
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In the digital clock project, what type of counter is used to count to 59 seconds?
A:
MOD-60
B:
MOD-6
C:
BCD
D:
BCD followed by a MOD-6
Answer: D
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What are two ways to remember the current state of a counter in VHDL?
A:
With FUNCTIONS and PROCESS
B:
With counters and timers
C:
With SIGNAL and VARIABLE
D:
With bit types
Answer: C
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In the frequency counter, when is the new count stored in the display register?
A:
After disabling the counter
B:
When the count buffer is full
C:
After the sample interval is set
D:
When the timing and control block has put it there
Answer: A
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Which is not a step in strategic planning for HDL development?
A:
There must be a way to test each piece.
B:
Each block must fit together to make up the whole system.
C:
The names of each input and output must be known.
D:
The exact operation of each block must be thoroughly defined and understood.
Answer: C
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