Exercise: Digital System Projects Using Hdl

Questions for: Digital System Projects Using Hdl

For the frequency counter, which is not a control signal from the control and timing block?
A:
Clear
B:
Enable
C:
Reset
D:
Store
Answer: C
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In the keypad application, just after the 4 ms mark the simulation imitates the release of the key by changing the column value back to F hex, which causes the d output to go into its Hi-Z state. On the next rising clock edge, what happens to dav?
A:
It goes HIGH.
B:
It goes LOW.
C:
It goes to Hi-Z.
D:
It goes to 1111H.
Answer: B
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When designing an HDL digital system, which is the worst mistake one can make?
A:
Concluding that a fundamental block works perfectly
B:
Failing to provide proper documentation
C:
Adding blocks of code prior to testing them
D:
Overlooking a possible VARIABLE
Answer: A
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List three basic blocks in the digital clock project.
A:
MOD-60, MOD-12 counters
B:
MOD-5, MOD-10, MOD-12 counters
C:
MOD-60, MOD-10 counters
D:
MOD-6, MOD-12, and MOD-10 counters
Answer: D
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In the frequency counter, what is the function of the Schmitt trigger circuit?
A:
To reduce input noise
B:
To condition the input signal
C:
To convert non-square waveforms
D:
To provide a usable signal to the display unit
Answer: C
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