Assertion (A): In a serial in-serial out shift register, access is available only to the left most or right most flip flops

Reason (R): If the output of a shift register is feedback to serial input it can be used as a ring counter.

A twisted ring counter consisting of 4 FF will have

A clock signal driving a 6-bit ring counter has a frequency of 1 MHz. How long is each timing bit high?

A two-input OR gate is designed for positive logic. However, it is operated with negative logic. The resulting logic operation will then be

In 8085 microprocessor, which of the following is not vectored interrupt?