Exercise: Digital Electronics

Questions for: Digital Electronics

Minimum number of 2-input NAND gates required to implement the function F = (x + y) (Z + W) is
A:
3
B:
4
C:
5
D:
6
Answer: B

F = (x + y) (z + w) = xy.(z + w)

= xyz + xyw

= minimum no. of 2 input NAND gate.

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The output of a half adder is
A:
SUM
B:
CARRY
C:
SUM and CARRY
D:
none of the above
Answer: C

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If the functions w, x, y, z are as follows.
w = R + PQ + RS ,
x = PQR S + PQR S + PQ R S


Then
A:
w = z x = z
B:
w = z, x = y
C:
w = y
D:
w = y = z
Answer: A

Use k-map, then it will be easy.

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A full adder can be made out of
A:
two half adders
B:
two half adders and a OR gate
C:
two half adders and a NOT gate
D:
three half adders
Answer: B

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For the truth table of the given figure Y =
A:
A + B + C
B:
A + BC
C:
A
D:
B
Answer: D

Y = A B C + A B C + AB C + A B C = A B (C + C) + A B (C + C) = A B + AB = B(A + A) = B.

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