Exercise: Digital Electronics

Questions for: Digital Electronics

A 4 bit ripple counter uses flip flops with propagation delay of 50 ns each. The maximum clock frequency which can be used is
A:
5 MHz
B:
10 MHz
C:
20 MHz
D:
25 MHz
Answer: A

Time delay = 50 x 4 x 10-9s,

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In the figure, the LED
A:
emits light when both S1 and S2 are closed
B:
emits light when both S1 and S2 are open
C:
emits light when only S1 and S2 is closed
D:
does not Emit light, irrespective of the switched positions
Answer: D

To emit the light, it is necessary NAND gate output is zero, for NAND O/P zero. Both the I/O must be height. And it is not possible in any case.

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The counter shown in the given figure is built using 4 -ve edge triggered toggle FFs. The FF can be set asynchronously when R = 0. The combinational logic required to realize a modulo-13 counter is
A:
F = Q4 Q3 Q2 Q1
B:
F = Q4 + Q3 + Q2 + Q1
C:
F = Q4 + Q3 + Q2 + Q1
D:
F = Q4Q3Q2Q1
Answer: A

Counter is modulo-13, it will count up to 15 but due to mod-13, it will be reset at 13, (13)10 = (1101 )2 = Q4 Q3 Q2 Q1.

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A counter has a modulus of 10. The number of flip flops is
A:
10
B:
5
C:
4
D:
3
Answer: C

23 = 8 and 24 = 16 Therefore 4 flip-flops are needed. Some states will be skipped to give a modulus of 10.

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A ripple counter has 4 bits and uses flip flops with propagation delay time of 25 ns. The maximum possible time for change of state will be
A:
25 ns
B:
50 ns
C:
75 ns
D:
100 ns
Answer: D

In ripple counter all the delays are added.

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