Exercise: Digital Electronics

Questions for: Digital Electronics

Assertion (A): The TTL output acts as a current sink in low state

Reason (R): The TTL input current is largest in low state.

A:
Both A and R are correct and R is correct explanation of A
B:
Both A and R are correct but R is not correct explanation of A
C:
A is true, R is false
D:
A is false, R is true
Answer: B
No answer description is available. Let's discuss.
In a synchronous counter all flip flops are clocked together.
A:
True
B:
False
C:
D:
Answer: A
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In a flip flop which input determines the state to which output will transistion?
A:
Control input
B:
Clock input
C:
Both control and clock input
D:
Either control or clock input
Answer: A
No answer description is available. Let's discuss.

Assertion (A): Boolean expressions can be easily simplified using Karnaugh map.

Reason (R): Karnaugh map can be drawn for minterms as well as max terms.

A:
Both A and R are correct and R is correct explanation of A
B:
Both A and R are correct but R is not correct explanation of A
C:
A is true, R is false
D:
A is false, R is true
Answer: B
No answer description is available. Let's discuss.
Time delay of a TTL standard family is about
A:
180 ns
B:
50 ns
C:
18 ns
D:
3 ns
Answer: C
No answer description is available. Let's discuss.
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