The 74LS382 ALU is a 24-pin arithmetic/logic unit.

The carry-out of a binary adder is identified using the summation symbol, sigma.

The VHDL compiler requires libraries to be specified at the beginning of the code if components from those libraries are being used.

Full adders can add two numbers and need not have a carry input or a carry output.

When the 2's-complement system is used, the number to be subtracted is changed to its 2's complement and then added to the minuend.