Exercise: Digital Arithmetic Operations And Circuits

Questions for: Digital Arithmetic Operations And Circuits

In VHDL, what is a GENERATE statement?
A:
The start statement of a program
B:
Not used in VHDL or ADHL
C:
A way to get the computer to generate a program from a circuit diagram
D:
A way to tell the compiler to replicate several components
Answer: D
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Could the sum output of a full-adder be used as a two-bit parity generator?
A:
Yes
B:
No
C:
D:
Answer: A
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An input to the mode pin of an arithmetic/logic unit (ALU) determines if the function will be:
A:
one's-complemented
B:
arithmetic or logic
C:
positive or negative
D:
with or without carry
Answer: B
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The carry propagation delay in 4-bit full-adder circuits:
A:
is cumulative for each stage and limits the speed at which arithmetic operations are performed
B:
is normally not a consideration because the delays are usually in the nanosecond range
C:
decreases in direct ratio to the total number of full-adder stages
D:
increases in direct ratio to the total number of full-adder stages, but is not a factor in limiting the speed of arithmetic operations
Answer: A
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A full-adder adds ________.
A:
two single bits and one carry bit
B:
two 2-bit binary numbers
C:
two 4-bit binary numbers
D:
two 2-bit numbers and one carry bit
Answer: A
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