Exercise: Analog Electronics

Questions for: Analog Electronics

In a class C operation VCC = 40 V and VCE(sat) = 0.4 V. The efficiency is
A:
90%
B:
49.5%
C:
1%
D:
0.5%
Answer: A
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Assertion (A): The ac load line is different from dc load line

Reason (R): The ac load resistance seen by collector and emitter is different from dc load resistance

A:
Both A and R are correct and R is correct explanation for A
B:
Both A and R are correct but R is not correct explanation for A
C:
A is correct R is wrong
D:
A is wrong R is correct
Answer: A
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Power transistors are invariably provided with
A:
soldered connections
B:
heat sink
C:
metallic casing
D:
none of the above
Answer: B
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In figure VCE (sat) = 0.1 V. Then IC (sat) =
A:
10 mA
B:
20 mA
C:
30 mA
D:
40 mA
Answer: B
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Assertion (A): Electric coupling, magnetic coupling and ground loop can cause unwanted high frequency oscillations.

Reason (R): Hartley oscillator uses a tapped inductor

A:
Both A and R are correct and R is correct explanation for A
B:
Both A and R are correct but R is not correct explanation for A
C:
A is correct R is wrong
D:
A is wrong R is correct
Answer: B
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